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max11190 4-channel, dual, simultaneous sampling, 2.2v to 3.6v, 12-bit, 3msps sar adc in tiny 3mm x 3mm tqfn package 19-6743; rev 2; 12/14 for related parts and recommended products to use with this part, refer to www.maximintegrated.com/max11190.related . ordering information appears at end of data sheet. general description the max11190 is a 4-channel, dual, multiplexed, 12-bit, compact, high-speed, low-power, successive approxi - mation analog-to-digital converter (adc). this high- performance dual adc includes high-dynamic range sample-and-holds and a high-speed serial interface. this adc accepts a full-scale input from 0v to the reference voltage. the device features two dual, single-ended analog inputs connected to two adc cores using 2:1 muxs. the device also includes a separate supply input for data interface and dedicated inputs for reference voltage. this device operates from a 2.2v to 3.6v supply and consumes only 10.5mw at 3msps. the device includes full power-down mode and fast wake-up for optimal power management and a high-speed 3-wire serial inter - face. the 3-wire serial interface directly connects to spi, qspi?, and microwire ? devices without external logic. each of the two internal adcs has its own dedicated douta/doutb for faster data communication. excellent dynamic performance, low voltage, low power, ease of use, and small package size make this converter ideal for simultaneous data-acquisition applications, and for other applications that demand low power consump - tion and minimal space. the device is available in a 3mm x 3mm, 16-pin tqfn package and operates over the -40oc to +125oc tempera - ture range. applications motor control simultaneous data acquisition medical instrumentation process control beneits and features integration and packaging save space ? simultaneous sampling ? dual, 4-channel, single-ended 12-bit resolution adc (2 x 2) ? 16-pin, 3mm x 3mm tqfn package excellent performance ideal for motor control applications ? 72db snr ? 3msps conversion rate without pipeline delay ? external reference inputs ? wide -40c to +125c operation low power design simplifies power-supply requirements ? very low power consumption at 5a/ksps ? 10.5mw at 3msps ? 2.2v to 3.6v supply voltage ? 2.6a power-down current dual spi ports simplifies system design ? spi-/qspi-/microwire-compatible serial interface with two douta/doutb pins ? dedicated digital output supply allows serial interface to directly connect to 1.5v, 1.8v, 2.5v, or 3v digital systems qspi is a trademark of motorola, inc. microwire is a registered trademark of national semiconductor corporation functional diagram evaluation kit available cdac-a mux refa ain2a chsel ain1a sar-a output buffer cdac-b mux ain2b ain1b v dd ovdd gnd douta sar-b output buffer doutb control logic cs control logic sclk max11190 refb downloaded from: http:///
max11190 4-channel, dual, simultaneous sampling, 2.2v to 3.6v, 12-bit, 3msps sar adc in tiny 3mm x 3mm tqfn package www.maximintegrated.com maxim integrated 2 table of contents general description ............................................................................ 1 applications .................................................................................. 1 benefits and features .......................................................................... 1 functional diagram ............................................................................ 1 absolute maximum ratings ...................................................................... 4 package thermal characteristics ................................................................. 4 electrical characteristics ........................................................................ 4 typical operating characteristics ................................................................. 8 pin configuration ............................................................................. 10 pin description ............................................................................... 10 typical operating circuit ........................................................................ 11 detailed description ........................................................................... 12 serial interface ................................................... .......................... 12 analog input ................................................... ............................ 12 adc transfer function ................................................... .................... 13 operation modes ................................................... ........................ 13 power-down mode ................................................... .................... 13 entering power-down mode ................................................... ............. 13 exiting power-down mode ................................................... .............. 14 supply current vs. sampling rate ................................................... ........... 14 dual-channel operation .................................................. ................... 15 14-cycle conversion mode ................................................... ................ 15 applications information ........................................................................ 15 layout, grounding, and bypassing .................................................. ........... 15 choosing an input amplifier ................................................... ............... 15 choosing a reference ................................................... .................... 16 definitions ................................................................................... 17 integral nonlinearity ................................................... ...................... 17 differential nonlinearity ................................................... .................... 17 offset error ................................................... ............................. 17 gain error ................................................... .............................. 17 aperture jitter ................................................... ........................... 17 aperture delay ................................................... .......................... 17 aperture delay matching .................................................. ................... 17 signal-to-noise ratio (snr) ................................................... ............... 17 signal-to-noise ratio and distortion (sinad) ................................................... .. 17 total harmonic distortion ................................................... .................. 17 spurious-free dynamic range (sfdr) ................................................... ....... 17 downloaded from: http:///
max11190 4-channel, dual, simultaneous sampling, 2.2v to 3.6v, 12-bit, 3msps sar adc in tiny 3mm x 3mm tqfn package www.maximintegrated.com maxim integrated 3 table of contents ( continued) list of figures full-power bandwidth ................................................... ..................... 17 full-linear bandwidth ................................................... ..................... 17 intermodulation distortion ................................................... .................. 17 ordering information .......................................................................... 18 chip information .............................................................................. 18 package information .......................................................................... 18 revision history .............................................................................. 19 figure 1. interface signals for maximum throughput .................................................. 7 figure 2. setup time after sclk falling edge ....................................................... 7 figure 3. hold time after sclk falling edge ........................................................ 7 figure 4. sclk falling edge douta/doutb three-state ............................................. 7 figure 5. analog input circuit ................................................................... 12 figure 6. normal mode ........................................................................ 13 figure 7. entering power-down mode ............................................................. 13 figure 8. exiting power-down mode .............................................................. 14 figure 9. adc transfer function ................................................................. 14 figure 10. supply current vs. sample rate (normal operating m ode) ................................... 14 figure 11. supply current vs. sample rate (device powered dow n between conversions) .................. 14 figure 12. channel select timing diagram ......................................................... 15 figure 13. 14-clock cycle operation .............................................................. 15 figure 14. typical application circuit .............................................................. 16 downloaded from: http:///
max11190 4-channel, dual, simultaneous sampling, 2.2v to 3.6v, 12-bit, 3msps sar adc in tiny 3mm x 3mm tqfn package www.maximintegrated.com maxim integrated 4 electrical characteristics (v dd = +2.2v to +3.6v, refa = refb = v dd , ovdd = v dd , unless otherwise noted. f sclk = 48mhz, 3msps, 50% duty cycle. reference pins are independent, c douta/doutb = 10pf. t a = -40oc to 125oc, unless otherwise noted. typical values are at t a = +25oc.) (note 2) v dd to gnd ....................................................................... -0.3v to +4v ain1a, ain2a to gnd .... -0.3v to the lower of (v dd + 0.3v) and +4.0v refa, ovdd to gnd .... -0.3v to the lower of (v dd + 0.3v) and +4.0v ain1b, ain2b to gnd .... -0.3v to the lower of (v dd + 0.3v) and +4.0v refb to gnd ................. -0.3v to the lower of (v dd + 0.3v) and +4.0v cs , sclk to gnd ..... -0.3v to the lower of (v ovdd + 0.3v) and +4.0v chsel to gnd ......... -0.3v to the lower of (v ovdd + 0.3v) and +4.0v douta to gnd ........... -0.3v to the lower of (v ovdd + 0.3v) and +4.0v doutb to gnd .......... -0.3v to the lower of (v ovdd + 0.3v) and +4.0v multilayer board max power dissipation (t a = +70oc) tqfn (derate 20.8mw/oc above +70oc) .................. 1667mw operating temperature range .......................... -40oc to +125oc storage temperature range ............................. -65oc to +150oc lead temperature (soldering, 10s) ................................. +300oc soldering temperature (reflow) ....................................... +260oc absolute maximum ratings stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. package thermal characteristics tqfn junction-to-ambient thermal resistance ( ja ) .......... 48c/w junction-to-case thermal resistance ( jc ) ............... 10c/w (note 1) note 1: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four-layer board. for detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial . parameter symbol conditions min typ max units dc accuracy resolution 12 bit 12 bits integral nonlinearity inl 1 lsb differential nonlinearity dnl no missing codes over temperature 1 lsb offset error 1 4.0 lsb gain error excluding offset and reference errors 1 4.0 lsb total unadjusted error tue 1.5 lsb channel-to-channel offset matching 0.3 lsb channel-to-channel gain matching 0.3 lsb dynamic performance signal-to-noise plus distortion (note 3) sinad f in = 1mhz 70 72 db signal-to-noise ratio snr f in = 1mhz 70.5 72 db total harmonic distortion thd f in = 1mhz -85 -75 db spurious-free dynamic range sfdr f in = 1mhz 76 85 db intermodulation distortion imd f in1 = 1.0003mhz, f in2 = 0.99955mhz -84 db full-power bandwidth -3db point 40 mhz full-linear bandwidth sinad > 68db 2.5 mhz small-signal bandwidth 45 mhz crosstalk channel to channel -90 db downloaded from: http:///
max11190 4-channel, dual, simultaneous sampling, 2.2v to 3.6v, 12-bit, 3msps sar adc in tiny 3mm x 3mm tqfn package www.maximintegrated.com maxim integrated 5 electrical characteristics (continued) (v dd = +2.2v to +3.6v, refa = refb = v dd , ovdd = v dd , unless otherwise noted. f sclk = 48mhz, 3msps, 50% duty cycle. reference pins are independent, c douta/doutb = 10pf. t a = -40oc to 125oc, unless otherwise noted. typical values are at t a = +25oc.) (note 2) parameter symbol conditions min typ max units conversion rate throughput 16 cycles 0.03 3 msps conversion time 13 cycles 260 ns acquisition time t acq track time = 2.5 cycles 52 ns aperture delay from cs falling edge 4 ns aperture delay matching 150 ps aperture jitter 15 ps serial-clock frequency f clk 0.48 48 mhz analog input (ain1a, ain2a, ain1b, and ain2b) input voltage range v ina ain1a and ain2a pins 0 v refa v v inb ain1b and ain2b pins 0 v refb v input leakage current i ila 0.002 1 a input capacitance c ain_ track 20 pf hold 4 external reference (refa and refb) input voltage range v refa v refb 1 v dd + 0.05 v input leakage current i ilr conversion stopped 0.005 1 a input capacitance c refa c refb 5 pf digital inputs (sclk, cs , chsel) input high voltage v ih 0.75 x v ovdd v input low voltage v il 0.25 x v ovdd v input hysteresis v hyst 0.15 x v ovdd %ovdd/ v dd input leakage current i il inputs at 0v or v ovdd 0.001 1 a input capacitance c in 2 pf digital output (douta and doutb) output high voltage v oh i source = 1ma 0.85 x v ovdd v output low voltage v ol i sink = 5ma 0.15 x v ovdd v three-state leakage current i ol 1.0 a three-state output capacitance(without pad metal) c out 5 pf downloaded from: http:///
max11190 4-channel, dual, simultaneous sampling, 2.2v to 3.6v, 12-bit, 3msps sar adc in tiny 3mm x 3mm tqfn package www.maximintegrated.com maxim integrated 6 electrical characteristics (continued) (v dd = +2.2v to +3.6v, refa = refb = v dd , ovdd = v dd , unless otherwise noted. f sclk = 48mhz, 3msps, 50% duty cycle. reference pins are independent, c douta/doutb = 10pf. t a = -40oc to 125oc, unless otherwise noted. typical values are at t a = +25oc.) (note 2) note 2: limits are 100% tested at t a = +25c. limits over the operating temperature range and relevant supply voltage range are guaranteed by design and characterization, unless otherwise noted. note 3: all timing specifications given are with a 10pf capacitor. note 4: guaranteed by design in characterization; not production tested. parameter symbol conditions min typ max units power supply positive supply voltage v dd v dd pin 2.2 3.6 v digital i/o supply voltage v ovdd ovdd pin 1.5 v dd v power-down current i pd leakage only, per supply pin 2.6 10 a positive supply current (full power mode) i dd f sample = 3msps, v ain = 0v, both adcs 6.8 ma positive supply current (full power mode), no clock i dd f sample = 3msps, v dd = +3v, both adcs 3.9 ma line rejection psr v dd = +2.2v to +3.6v, v ref = 2.2v 0.7 lsb/v timing characteristics quiet time t q (note 4) 4 ns cs pulse width t 1 (note 4) 10 ns cs fall to sclk setup t 2 (note 4) 5 ns cs falling until douta/doutb three-state disabled t 3 (note 4) 1 ns data access time after sclk falling edge t 4 v ovdd = 2.2v to 3.6v 15 ns v ovdd = 1.5v to 2.2v 16.5 sclk pulse-width low t 5 percentage of clock period (note 4) 40 60 % sclk pulse-width high t 6 percentage of clock period (note 4) 40 60 % data hold time from sclk falling edge t 7 figure 3 (note 4) 5 ns sclk falling until douta/doutb three-stated t 8 figure 4 (note 4) 2.5 14 ns t-power up 1 conversion cycle (note 4) 1 cycle downloaded from: http:///
max11190 4-channel, dual, simultaneous sampling, 2.2v to 3.6v, 12-bit, 3msps sar adc in tiny 3mm x 3mm tqfn package www.maximintegrated.com maxim integrated 7 figure 1. interface signals for maximum throughput figure 2. setup time after sclk falling edge figure 4. sclk falling edge douta/doutb three-state figure 3. hold time after sclk falling edge 12 3 45 67 89 10 11 12 13 14 15 16 16 1 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 doutadoutb sclk high impedance t 6 t 2 t 5 t 1 0 sample sample 00 (msb) t 3 t 4 t 7 t 8 t quiet t convert 1/f sample t acq cs high impedance v ih v il new data old data doutadoutb sclk t 4 v ih v il old data new data doutadoutb sclk t 7 high impedance doutadoutb sclk t 8 downloaded from: http:///
max11190 4-channel, dual, simultaneous sampling, 2.2v to 3.6v, 12-bit, 3msps sar adc in tiny 3mm x 3mm tqfn package maxim integrated 8 www.maximintegrated.com typical operating characteristics differential nonlinearity vs. digital output code (b) max11190 toc02b digital output code dnl (lsb) 3000 2000 1000 -0.5 0 0.5 1.0 -1.0 0 4000 f s = 3msps snr and sinad vs. analog input frequency max11190 toc05 f in (khz) snr and sinad (db) 1200 900 600 300 71 72 73 74 7570 0 1500 snr (b) snr (a) sinad (b) sinad (a) f s = 3msps offset error vs. temperature max11190 toc03 temperature (oc) offset error (lsb) 110 95 80 65 50 35 20 5 -10 -25 -2 -1 0 1 2 3 -3 -40 125 b a thd vs. analog input frequency max11190 toc06 f in (khz) thd (db) 1200 900 600 300 -95 -90 -85 -80 -100 0 1500 f s = 3msps b a gain error vs. temperature max11190 toc04 temperature (oc) gain error (lsb) 110 95 80 65 50 35 20 5 -10 -25 -2 -1 0 1 2 3 -3 -40 125 a b sfdr vs. analog input frequency max11190 toc07 f in (khz) thd (db) 1200 900 600 300 80 90 100 110 70 0 1500 f s = 3msps b a integral nonlinearity vs. digital output code (a) max11190 toc01a digital output code inl (lsb) 3000 2000 1000 -0.5 0 0.5 1.0 -1.0 0 4000 f s = 3msps integral nonlinearity vs. digital output code (b) max11190 toc01b digital output code inl (lsb) 3000 2000 1000 -0.5 0 0.5 1.0 -1.0 0 4000 f s = 3msps differential nonlinearity vs. digital output code (a) max11190 toc02a digital output code dnl (lsb) 3000 2000 1000 -0.5 0 0.5 1.0 -1.0 0 4000 f s = 3msps downloaded from: http:///
max11190 4-channel, dual, simultaneous sampling, 2.2v to 3.6v, 12-bit, 3msps sar adc in tiny 3mm x 3mm tqfn package maxim integrated 9 www.maximintegrated.com typical operating characteristics (continued) thd vs. input resistance max11190 toc08 r in () thd (db) 80 60 40 20 0 100 f s = 3msps f in = 1.0183mhz b a -95 -90 -85 -80 -75 -70 -100 total supply current vs. temperature max11190 toc10 temperature (oc) i vdd (ma) 110 95 80 65 50 35 20 5 -10 -25 5.2 5.4 5.6 5.8 6.05.0 -40 125 1mhz sine wave input (16384 point fft plot) (a) max11190 toc12a frequency (khz) amplitude (db) 1250 1000 750 500 250 -100 -80 -60 -40 -20 0 -120 0 1500 f s = 3msps f in = 1.0183mhz a hd3 = -90.6db a hd2 = -86.9db reference current vs. sampling rate max11190 toc09 f s (ksps) i ref (a) 2000 1500 1000 500 50 100 150 200 0 0 3000 2500 b a snr vs. reference voltage max11190 toc11 v ref (v) snr (db) 3.4 3.2 3.0 2.8 2.6 2.4 2.2 71.5 72.0 72.5 73.0 73.571.0 2.0 3.6 f s = 3msps f in = 1.0183mhz b a 1mhz sine wave input (16384 point fft plot) (b) max11190 toc12b frequency (khz) amplitude (db) 1250 1000 750 500 250 -100 -80 -60 -40 -20 0 -120 0 1500 f s = 3msps f in = 1.0183mhz a hd3 = -89.6db a hd2 = -86.3db downloaded from: http:///
max11190 4-channel, dual, simultaneous sampling, 2.2v to 3.6v, 12-bit, 3msps sar adc in tiny 3mm x 3mm tqfn package www.maximintegrated.com maxim integrated 10 pin description pin coniguration pin name function 1 douta serial-data output of adc a. douta changes state on sclks falling edge. 2 doutb serial-data output of adc b. doutb changes state on sclks falling edge. 3 sclk serial-clock input. sclk drives the conversion process and clocks data out. 4 gnd ground. this pin must connect to a solid ground plane. 5 ain1a channel 1 of adc a 6 ain1b channel 1 of adc b 7 ain2a channel 2 of adc a 8 ain2b channel 2 of adc b 9 refa reference pin for adc a 10 refb reference pin for adc b 11, 12 v dd positive supply voltage 13 gnd ground. this pin must connect to a solid ground plane. 14 cs chip select (active-low). initiates power-up and acquisition on the falling edge. 15 chsel channel select pin referring to ain1a/ain1b and ain2a/ain2b. set chsel low to select ain1a/ ain1b for conversion. 16 ovdd digital i/o supply voltage (cs , chsel, douta, doutb, sclk). bypass to gnd with a 4.7f ceramic capacitor. ep exposed pad, internally connected to ground. connect to a solid ground plane. 1516 14 13 5 6 7 sclk gnd 8 douta refbrefa v dd 13 cs ep* *ep = exposed pad. 4 12 10 9 chsel ovdd ain2bain2 a ain1bain1 a dout bv dd 2 11 gnd tqfn max11190 top view + downloaded from: http:///
max11190 4-channel, dual, simultaneous sampling, 2.2v to 3.6v, 12-bit, 3msps sar adc in tiny 3mm x 3mm tqfn package www.maximintegrated.com maxim integrated 11 typical operating circuit ovdd analog inputs analog inputs ain1aain1b ain2a ain2b refarefb +3v gnd gnd (ep) chsel doutb douta cs sclk misoa cpu misob +3v +3v v dd +3v max11190 downloaded from: http:///
max11190 4-channel, dual, simultaneous sampling, 2.2v to 3.6v, 12-bit, 3msps sar adc in tiny 3mm x 3mm tqfn package www.maximintegrated.com maxim integrated 12 detailed description the max11190 is a 3msps, 12-bit, low-power, single- supply, dual, multiplexed simultaneous-sampling adc. the device operates from a 2.2v to 3.6v supply and consumes only 16.4mw (v dd = 3v) /10.5mw (v dd = 2.2v) at 3msps. this device is capable of sampling at full rate when driven by 48mhz. the max11190 provides a separate digital supply input (ovdd) to power the digital interface enabling communication with 1.5v, 1.8v, 2.5v, or 3v digital systems. the conversion results for each of the two integrated adcs appear at douta and doutb, msb first, with a leading zero followed by the 12-bit results followed by two trailing zeros. see figure 1 . each adc core has an independent reference input. the input signal range for analog inputs is defined as 0v to v ref (v ref of respective core) with respect to gnd. this device includes a power-down feature allowing minimized power consumption at 5a/ksps for lower throughput rates. the wake-up and power-down feature is controlled by using the spi interface as described in the operation modes section. serial interface the max11190 features a 3-wire serial interface that directly connects to spi, qspi, and microwire devices without external logicdouta and doutb need to be received by the host at the same time. figure 1 shows the interface signals for a single conversion frame to achieve maximum throughput. the falling edge of cs defines the sampling instant. once cs transitions low, the external clock signal (sclk) con - trols the conversion. each of the two sar cores of this device successively extracts binary-weighted bits in every clock cycle. the msb appears on the data bus during the 2nd clock cycle with a delay outlined in the timing specifications. all extracted data bits appear successively on the data bus with the lsb appearing during the 13th clock cycle for 12-bit operation. the serial data stream of conversion bits is preceded by a leading zero and succeeded by trailing zeros. the data outputs (douta and doutb) go into high-impedance state during the 16th clock cycle. to sustain the maximum sample rate, all devices have to be resampled immediately after the 16th clock cycle. for lower sample rates, the cs falling edge can be delayed leaving douta/doutb in a high-impedance condition. pull cs high after the 10th sclk falling edge (see the operation modes section). analog input the max11190 produces digital outputs that correspond to the analog input voltages within the specified operating range of 0 to v ref . figure 5 shows an equivalent circuit for the analog input ain1a/ain1b/ain2a/ain2b. internal protection diodes d1/ d2 confine the analog input voltage within the power rails (v dd , gnd). the analog input voltage can swing from v gnd - 0.3v to v dd + 0.3v without damaging the device. the electric load presented to the external stage driving the analog input varies depending on which mode the adc is in: track mode vs. conversion mode. in track mode, the internal sampling capacitor, c s (16pf), must be charged through the resistor, r (50?), to the input voltage. for faith - ful sampling of the input, the capacitor voltage on cs has to settle to the required accuracy during the track time. the source impedance of the external driving stage in conjunction with the sampling switch resistance affects the settling performance. the thd vs. input resistance graph in the typical operating characteristics shows thd sensi - tivity as a function of the signal source impedance. keep the source impedance at a minimum for high-dynamic per - formance applications. use a high-performance op amp, such as the max4430, to drive the analog input, thereby decoupling the signal source and the adc. while the adc is in conversion mode, the sampling switch is open presenting a pin capacitance, c p (c p = 5pf), to the driving stage. see the applications information section for information on choosing an appropriate buffer for the adc. figure 5. analog input circuit c p a in1a/ain1b/ a in2a/ain2b v dd a in d2 d1 r c s switch closed in track modeswitch open in conversion mode downloaded from: http:///
max11190 4-channel, dual, simultaneous sampling, 2.2v to 3.6v, 12-bit, 3msps sar adc in tiny 3mm x 3mm tqfn package www.maximintegrated.com maxim integrated 13 adc transfer function the output format is straight binary. the code transitions midway between successive integer lsb values such as 0.5 lsb, 1.5 lsb, etc. the lsb size is v ref /2 12 . the ideal transfer characteristic is shown in figure 9 . operation modes the ic offers two modes of operation: normal mode and power-down mode. the logic state of the cs signal dur - ing a conversion activates these modes. the power-down mode can be used to optimize power dissipation with respect to sample rate. normal mode in normal mode, the device is powered up at all times, thereby achieving its maximum throughput rates. figure 6 shows the timing diagram of this device in normal mode. the falling edge of cs samples the analog input signal, starts a conversion, and frames the serial-data transfer. to remain in normal mode, keep cs low until the falling edge of the 10th sclk cycle. pulling cs high after the 10th sclk falling edge keeps the part in normal mode. however, pulling cs high before the 10th sclk falling edge terminates the conversion, both douta/doutbs go into high-impedance mode, and the device enters power- down mode. see figure 7 . power-down mode in power-down mode, all bias circuitry is shut down draw - ing typically only 2.6a of leakage current. to save power, put the device in power-down mode between conver - sions. using the power-down mode between conversions is ideal for saving power when sampling the analog input infrequently. entering power-down mode to enter power-down mode, drive cs high between the 2nd and 10th falling edges of sclk (see figure 7 ). by pulling cs high, the current conversion terminates and both douta/doutb enter high impedance. figure 6. normal mode figure 7. entering power-down mode 12345678 91 01 11 21 31 41 51 6 sclk pull cs high after the 10th sclk falling edge keep cs low until after the 10th sclk falling edge cs doutadoutb valid data high impedance high impedance 12345678 91 01 11 21 31 41 51 6 high impedance invalid data sclk cs doutadoutb invalid data or high impedanc eh igh impedance pull cs high after the 2nd and before the 10th sclk falling edge downloaded from: http:///
max11190 4-channel, dual, simultaneous sampling, 2.2v to 3.6v, 12-bit, 3msps sar adc in tiny 3mm x 3mm tqfn package www.maximintegrated.com maxim integrated 14 figure 9. adc transfer function figure 8. exiting power-down mode exiting power-down mode to exit power-down mode, implement one dummy conver - sion by driving cs low for at least 10 clock cycles (see figure 8 ). the data on douta/doutb is invalid during this dummy conversion. the first conversion following the dummy cycle contains a valid conversion result. the power-up time equals the duration of the dummy cycle, and is dependent on the clock frequency. the power-up time for this device (48mhz sclk) is 333ns. supply current vs. sampling rate for applications requiring lower throughput rates, the user can reduce the clock frequency (f sclk ) to lower the sam - ple rate. figure 10 shows the typical supply current (i vdd ) as a function of sample rate (f s ) for the device. the part operates in normal mode and is never powered down. the user can also power down the adc between conver - sions by using power-down mode. figure 11 shows this device as the sample rate is reduced, the device remains in the power-down state longer and the average supply current (i vdd ) drops accordingly. figure 10. supply current vs. sample rate (normal operating mode) figure 11. supply current vs. sample rate (device powered down between conversions) 12 34 56 78 9 10 11 12 13 14 15 16 n1 23 45 67 89 10 11 12 13 14 15 16 high impedance high impedance high impedance sclk cs doutadoutb invalid data (dummy conversion) valid data fs - 1.5 x lsb output code analoginput (lsb) 111...111111...110 111...101 0 123 2 n -2 2 n -1 2 n 000...000 000...001 000...010 full scale (fs): ain1a/ain1b/ain2a/ain2b = refa/refb n = resolution f s (ksps) i vdd (ma) 2000 2500 1000 1500 1 2 3 4 5 6 7 8 9 10 0 0 3000 v dd = 3v f sclk = variable 16 cycles/conversion 500 f s (ksps) i vdd (ma) 800 600 400 200 1 2 3 4 5 60 0 1000 v dd = 3v f sclk = 48mhz downloaded from: http:///
max11190 4-channel, dual, simultaneous sampling, 2.2v to 3.6v, 12-bit, 3msps sar adc in tiny 3mm x 3mm tqfn package www.maximintegrated.com maxim integrated 15 dual-channel operation the max11190 features dual simultaneous-sampling adcs each with two multiplexed channels. this device uses a channel-select (chsel) input to select between analog input ain1a/ain1b (chsel = 0) or ain2a/ain2b (chsel = 1). as shown in figure 12 , the chsel signal is required to change between the 2nd and 12th clock cycle within a regular conversion to guarantee proper switching between channels. 14-cycle conversion mode the ic can operate with 14 cycles per conversion. figure 13 shows the corresponding timing diagram. observe that douta/doutb does not go into high- impedance mode. also, observe that t acq needs to be sufficiently long to guarantee proper settling of the analog input voltage. see the electrical characteristics table for t acq requirements and the analog input section for a description of the analog inputs. applications information layout, grounding, and bypassing for best performance, use pcbs with a solid ground plane. ensure that digital and analog signal lines are separated from each other. do not run analog and digital (especially clock) lines parallel to one another or digital lines underneath the adc package. noise in the v dd power supply, ovdd, and refa/refb affects the adcs performance. bypass the v dd , ovdd, and refa/ refb to ground with 0.1f and 10f bypass capacitors. minimize capacitor lead and trace lengths for best supply- noise rejection. choosing an input ampliier it is important to match the settling time of the input ampli - fier to the acquisition time of the adc. the conversion results are accurate when the adc samples the input signal for an interval longer than the input signals worst- case settling time. by definition, settling time is the interval figure 12. channel select timing diagram figure 13. 14-clock cycle operation 1 data channel ain1a data channel ain2a sclk chsel doutadoutb cs data channel ain1b data channel ain2b 23456 78 91 01 11 21 31 4151 6 12345 67 89 10 11 12 13 14 15 16 1 doutadoutb sclk (msb) sample sample 1/f sample t acq t convert cs 23 4 d10 d11 56 78 91 01 11 21 31 41 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 00 0 downloaded from: http:///
max11190 4-channel, dual, simultaneous sampling, 2.2v to 3.6v, 12-bit, 3msps sar adc in tiny 3mm x 3mm tqfn package www.maximintegrated.com maxim integrated 16 between the application of an input voltage step and the point at which the output signal reaches and stays within a given error band centered on the resulting steady-state amplifier output level. the adc input sampling capaci - tor charges during the sampling cycle, referred to as the acquisition period. during this acquisition period, the set - tling time is affected by the input resistance and the input sampling capacitance. this error can be estimated by looking at the settling of an rc time constant using the input capacitance and the source impedance over the acquisition time period. figure 14 shows a typical application circuit. the max4430, offering a settling time of 37ns at 16 bits, is an excellent choice for this application. see the thd vs. input resistance graph in the typical operating characteristics . choosing a reference for devices using an external reference, the choice of the reference determines the output accuracy of the adc. an ideal voltage reference provides a perfect initial accuracy and maintains the reference voltage indepen - dent of changes in load current, temperature, and time. considerations in selecting a reference include initial voltage accuracy, temperature drift, current source, sink capability, quiescent current, and noise. figure 14 shows a typical application circuit using the max6126 to provide the reference voltage. the max6033 and max6043 are also excellent choices. figure 14. typical application circuit max11190 max6126 ovdd v ovdd +3v sclk digital interface douta/ doutb chsel sck miso cs ss 0.1f 1f 10f 0.1f agnd ain1a/ ain1b in1a/in1b v dc 4 1 52 2 3 ain2a/ ain2b v dd 72 1 64 3 10f 0.1f 0.1f 0.1f +5v -5v 470pf cog capacitor 10 500 470pf cog capacitor 10f +5v 10f 0.1f 0.1f 10f refa outf in nr outsgnds gnd ep max4430 in2a/in2b v dc 4 1 5 3 0.1f +5v -5v 10 10f 0.1f 10f max4430 500 500500 100pf cog 100pf cog refb downloaded from: http:///
max11190 4-channel, dual, simultaneous sampling, 2.2v to 3.6v, 12-bit, 3msps sar adc in tiny 3mm x 3mm tqfn package www.maximintegrated.com maxim integrated 17 deinitions integral nonlinearity integral nonlin earity (inl) is the deviation of the values on an actual transfer function from a straight line. for these devices, the straight line is a line drawn between the end points of the transfer function after offset and gain errors are nulled. differential nonlinearity differe ntial nonlinearity (dnl) is the difference between an actual step width and the ideal value of 1 lsb. a dnl error specification of 1 lsb or less guarantees no miss - ing codes and a monotonic transfer function. offset error offset error is the deviation of the first code transition (00 . . . 000) to (00 . . . 001) from the ideal, that is, agnd + 0.5 lsb . gain error gain error is the deviation of the last code transition (111 . . . 110) to (111 . . . 111) from the ideal after adjusting for the offset error, that is, v ref - 1.5 lsb. aperture jitteraperture jitter (t aj ) is the sample-to-sample variation in the time between the samples. aperture delay aperture delay (t ad ) is the time between the falling edge of the sampling clock and the instant when an actual sample is taken. aperture delay matching aperture delay (t adm ) is the difference between the aper - ture delay between channel a and b measured at the fall - ing edge of the sampling clock for the sample taken from the identical analog input. signal-to-noise ratio (snr) snr is a dynamic figure of merit that indicates the con - verters noise performance. for a waveform perfectly reconstructed from digital samples, the theoretical maxi - mum snr is the ratio of the full-scale analog input (rms value) to the rms quantization error (residual error). the ideal, theoretical minimum analog-to-digital noise is caused by quantization error only and results directly from the adcs resolution (n bits): snr (db) (max) = (6.02 x n + 1.76) (db) in reality, there are other noise sources such as thermal noise, reference noise, and clock jitter that also degrade snr. snr is computed by taking the ratio of the rms signal to the rms noise. rms noise includes all spectral components to the nyquist frequency excluding the fun - damental, the first five harmonics, and the dc offset. signal-to-noise ratio and distortion (sinad) sinad is a dynamic figure of merit that indicates the con - verters noise and distortion performance. sinad is com - puted by taking the ratio of the rms signal to the rms noise plus distortion. rms noise plus distortion includes all spectral components to the nyquist frequency exclud - ing the fundamental and the dc offset: ( ) rms rms signal sinad ( db ) 20 log noise distortion ?? = ?? + ???? total harmonic distortion total harmonic distortion (thd) is the ratio of the rms sum of the first five harmonics of the input signal to the fundamental itself. this is expressed as: 2222 45 23 1 vvvv thd 20 log v ?? +++ ?? = ?? ?? ?? ?? where v 1 is the fundamental amplitude and v 2 Cv 5 are the amplitudes of the 2nd- through 5th-order harmonics. spurious-free dynamic range (sfdr) sfdr is a dynamic figure of merit that indicates the low - est usable input signal amplitude. sfdr is the ratio of the rms amplitude of the fundamental (maximum signal component) to the rms value of the next largest spurious component, excluding dc offset. sfdr is specified in decibels with respect to the carrier (dbc). full-power bandwidth full-power bandwidth is the frequency at which the input signal amplitude attenuates by 3db for a full-scale input. full-linear bandwidth full-linear bandwidth is the frequency at which the sinad is equal to a specified value. intermodulation distortion an y device with nonlinearities creates distortion products when two sine waves at two different frequencies (f 1 and f 2 ) are applied into the device. intermodulation distortion (imd) is the total power of the im2 to im5 intermodula - tion products to the nyquist frequency relative to the total input power of the two input tones, f 1 and f 2 . the indi - vidua l input tone levels are at -6dbfs. downloaded from: http:///
max11190 4-channel, dual, simultaneous sampling, 2.2v to 3.6v, 12-bit, 3msps sar adc in tiny 3mm x 3mm tqfn package www.maximintegrated.com maxim integrated 18 ordering information note: all devices are specified over the -40oc to +125oc operating temperature range. +denotes lead(pb)-free/rohs-compliant package. *ep = exposed pad. package information for the latest package outline information and land patterns (footprints), go to www.maximin teg rated.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. chip information process: cmos part pin-package bits speed max11190ate+ 16 tqfn-ep* 12 3msps package type package code outline no. land pattern no. 16 tqfn-ep t1633mk+5 21-0136 90-0032 downloaded from: http:///
maxim integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim integrated product. no circuit patent licenses are implied. maxim integrated reserves the right to change the circuitry and speciications without n otice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. maxim integrated and the maxim integrated logo are trademarks of maxim integrated products, inc. max11190 4-channel, dual, simultaneous sampling, 2.2v to 3.6v, 12-bit, 3msps sar adc in tiny 3mm x 3mm tqfn package ? 2014 maxim integrated products, inc. 19 revision history revision number revision date description pages changed 0 6/13 initial release 1 2/14 updated package thermal characteristics and package information 4, 18 2 12/14 updated beneits and features section 1 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim integrateds website at www.maximintegrated.com. downloaded from: http:///

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